The present invention relates to programming of flash memories and, more particularly, to a method of programming a flash memory twice or more without erasing the memory cells between programmings.
Flash memories are a popular storage medium used in many applications, such as PDA-s, Mobile-Phones, Digital Cameras, Digital Audio Players, flash disks, etc. The properties of flash memory, making it so popular, include the fact that flash memory is non-volatile, meaning that no power is needed to maintain the information stored in the memory. In addition, flash memory offers fast read access times. Another feature of flash memory is that when packaged in a memory card, it is enormously durable, being able to withstand intense pressure, extremes of temperature, and even immersion in water.
Flash memories can be written and erased multiple times. (For historical reasons, writing to a flash memory often is called “programming” the flash memory. The terms “programming” and “writing” are used interchangeably herein.) However, the performance of a flash memory degrades as a function of the number of write erase cycles of the device. As the size of the feature of the integrated circuits that constitute a flash memory become increasingly smaller, the limitation on the number of erase cycles that a flash memory can tolerate before it starts to become unreliable becomes more and more severe and may fall to ˜102-104 erase cycles. In a modern environment, with ever increasing use of high bandwidth data, the number of write erase cycles of a device is a real limitation on its expected life time.
A flash memory system that is capable of withstanding a larger number of write-erase cycles before its performance degrades would have significant advantages over conventional flash memory systems.
A naive way of extending the write-erase (W/E) cycles of a flash memory may be achieved by adding cells. Increasing the number of Word Lines (WL) or cells by a factor of ‘t’ reduces the number of W/E cycles by a factor of ‘t’ for programming the same amount of information. But this is a very inefficient solution.
A more attractive solution is to devise a method that allows several programming cycles of a page of a flash memory before the page is erased. One conventional solution is as follows, for a single bit per cell flash memory (usually referred to misleadingly as a “Single Level Cell”, or “SLC” flash memory) in which an erased cell represents a “1” bit and a programmed cell represents a “0” bit.
The encoding of the input data for the first programming cycle is given by:
TABLE 1InformationCode00011011011011011111For example, the two input bits “00” are represented in the flash memory by three cells programmed to store the value “011”. The encoding for the second programming cycle is given by the matrix depicted in the following table:
TABLE 2Code in first programmingInformation01110111011100011100100100010101010100101000100111000111000000000111For each set of two new information bits and three bits already programmed in the three cells, Table 2 provides a new value for the three cells. The transition is made such that each cell can move from erase state “1” to programmed state“0” from the bits of the first programming operation but not the other way around, i.e., setting a programmed cell that stores “0” to an erased cell that stores “1”. For example, if the three cells store the value “110” and it is desired to program the information sequence “01” then the value to store in the three cells should be “010”, which means that the first cell is programmed to store “0” and the other two cells remain in their states as programmed in the first programming cycle.
It is quite simple to implement a short code with this scheme. The overhead (defined below) of this code is 50%. To decrease the number of flash cells needed to store the input data, it would be highly advantageous to have a similar scheme that has less overhead.